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Keynote & Invited Speakers(2013)

Plenary Session

Prof. Ivar Giaever, Nobel Laureate and Professor of Rensselaer Polytechnic Institute, USA

Dr. Ghavam Shahidi,  IBM Fellow and Director of Silicon Technology, IBM Thomas J. Watson Research Center, USA

Dr. Peng Bai, Vice President, Technology and Manufacturing Group, Intel, USA

* Invited Speech ** Keynote Speech

Symposium I: Device Engineering and Technology

**H. lwai, Professor, Tokyo Institute of Technology, Japan

Future of Nano CMOS Technology

**Prof. Philip Wong
, Professor, Stanford University, USA

Directed Self-Assembly for Random Logic Circuits - An Opportunity for Design Tool Development

*Bich-yen Nguyen, SOITEC, USA

ETSOI technology

*
C.-H. Chien, Professor, Taiwan University, China

High Performance Ge/Si Heterojunctions and Ge MOSFETs Directly on Si Substrate

*Chwan-Ying Lee, Deputy R&D Director, ITRI, China

Innovative Wideband Gap Power Devices Achievements in ITRI

*D.S.Ang, Professor, NTU, Singapore

Negative-bias Temperature instability - Insight from dynamic stress experiments


High Performance Bulk Planar 20nm CMOS Technology for Low Power Mobile Applications

*Kevin Chen, Professor, Hong Kong University of Science and Technology, China 

Device Technologies for GaN Power Integrated Circuit

*Myung-Hee Na, Manager,  IBM, USA

Impact of mobility on sub-Vt regions in highly strained MOSFET

*
Moongyu Jang
, Principal Researcher, Electronics and Telecommunications Research Institute, Korea 

Silicon nanowire thermoelectric device

*P. D. Ye, Professor, Purdue University, USA

III-V MOSFETs: From Planar to 3D/4D

*Rino Choi, Professor, Inha University, Korea

Characterization and modeling of trap states in polysilicon channel material

*
R. S. Wang
, Professor, Peking University, China

Recent Advances in Dynamic Variability in Nanoscale MOS Devices

*Seok-Hee Lee, Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea 

Fabrication and characterization of junctionless transistors

*Frank Yang, Qualcom, USA

Advanced CMOS technology

*Huiling Shang, IBM, USA

*Seong-Ook Jung, Professor, Yongsei University, Korea

Comparative Study for SRAM Bitcells in Near- and Sub-threshold Region

*Tsu-Kun Ku, Division Director, ITRI, China

TSV Process intergration for 3DIC Application

*
Zhiqiang Wei
, Staff engineer, Panasonic, Japan

Development of highly reliable ReRAM based on the physical model

Symposium II: Lithography and Patterning

**Cheng Bai Xu, Senior R&D Manager, DOW Chemical Company, USA

EUV Chemically Amplified Resists – Progress toward the ITRS roadmap targets

**Dr. Mike Rieger, CTO, Synopsys, USA

Lithography opportunities for advanced IC scaling

**Dr. Geoffrey Yeap, VP, Qualcom, USA

Advanced Technology-Design-Manufacturing Co-optimization for Smart Mobile Devices

**Dr. Luigi Capodieci, Fellow and Director, Global Foundries, USA

A roadmap for DFM and Physical Design at the limits of IC scaling

**Dr. Serdar MANAKLI, CEO, ASELTA Nanographics, France

Strategies for advanced Mask nodes: Resolution, Process & Cost Reduction

**Dr. Serge Tedesco, Program Manager, CEA-LETI, France

ML2 and DSA opportunities: Is there an alternative to Optics Forever?

*Dr. Edmund Lam, Professor, University of Hong Kong, China

Efficient Mask Synthesis with Augmented Lagrangian Methods in Computational Lithography

*Dr. Leo Pang, Senior Vice President, Luminescent Technologies, Inc

Solving Mask Requal Challenges in Advanced Wafer Fabs with Computational Metrology & Inspection (CMI) Technologies


*Dr. Joy Cheng, Research Staff, IBM Alamden Research Center, USA

Directed Self-Assembly for Extending Patterning Capability

*Dr. John Sturtevant, Director, Mentor Graphics, USA

Patterning Process Model Challenges for 14nm

*Dr. Kafai Lai, Senior scientist/Engineer, IBM semiconductor Research and Development Center, USA

Overview of Computational Techniques for Emerging Lithography Technologies

*Dr. Peng Liu, Sr. Principal Engineer, Brion, USA

Advanced modeling for full-chip low-k1 lithography simulations

*Dr. Zhibiao Mao, Member of Technical Staff, Shanghai Huali Microelectronics Corporation, China

Sub-Resolution Assist Features for Enhancing Lithographic Performance and Quality of Photomask

*Alek Chen, Director, ASML_ TDC Taiwan, China

EUVL to extend the Moore's Law

*Lin Qunying, Deputy director, Institute of Microelectronics, China

Development of Mask 3D Virtual Aberration Model to Predict Pattern Best Focus and Line Width Control

*Ralph R. Dammel, CTO, AZ Electronic Materials, Luxembourg

Directed Self Assembly: Progress in Bottom-Up Lithography

*Shinji Tarutani, Research Manager, Fujifilm Corporation, Japan

Negative Tone Development Process and Resist Materials with ArF Immersion Exposure Process

*Tooru Kimura, Technical Manager, JSR Corporation, Japan

Development status of EUV resist toward sub-20nmhp

*Xuelong Shi, Technical Director, Semiconductor Manufacturing International Corp, China

Critical Mask Related Aspects on Lithography Patterning at 28nm Node

*Yijian Chen, Associate Professor, Peking University, China

Understanding the critical challenges in implementation of self-aligned multiple patterning techniques for deep nano-scale IC 

*Yalin Xiong, GM of RAPID Group, KLA_tencor, USA

Mask Inspection in Era of 193nm and EUV Lithography

Symposium III: Dry & Wet Etch and Cleaning

**Subu Iyer, IBM Fellow, IBM, USA

**Dr. Richardo Ruiz, Research Staff Member, HGST, A Western Digital Company, USA

Pattern Formation and Pattern Transfer Strategies for ~ 10nm Lithography in Magnetic Recording Bit Patterned Media


*Dr. Efrain Altamirano Sanchez, Senior Research, IMEC, Belgium

Challenges for smoothing EUV photoresist line-width-roughness: plasma treatment from 40 to 22 nm half pitches

*Dr. Francesca Iacopi, Senior Research Fellow, Griffith University, Australia

Towards zero-damage patterning of porous dielectrics with cryogenic processes

*Dr. Hidetami Yaegashi, Senior Manager, Tokyo Electron LTD, Japan

Important Challenges in Double Patterning Process

*Dr. Jeremy Pereira, Research Engineer, Crocus Technology, France

Process challenges of MRAM technology integration

*
Dr. Qingyun Yang
, Principal Research Scientist, TEL, USA

Plasma etching patterning of FinFET


*Dr. Ying Xiao, Department Managet, TSMC, China

Etch challenges for 20nm technology and beyond

*Dr. Ying Zhang, Director, TSMC, Taiwan, China

The Plasma Etching Patterning of FinFET


Symposium IV: Thin Film Technology

**Alfred Grill, IBM Fellow, IBM T.J. Watson Research Center, USA

Advanced dielectrics for VLSI interconnects-State of the Art

**Mario Paniccia, Intel Fellow, Intel, USA

Silicon Photonics

**
Philips Wong
, Professor, Stanford University, USA

Emerging Memory Devices

*Anabela Veloso, Principle Engineer, IMEC, Belgium

Integration Challenges and Options of Replacement High-k Metal Gate Technology for (Sub-)22nm Technology Nodes

*Baozhen Li, Senior Technical Staff Member, IBM, USA

Engineering Cu Surface for Electromigration Reliability Enhancement

*Chao ZHAO,  Director of IC Advanced Process Center,  IMECAS, China

High-K last process for 22nm CMOS Technology

*Erik Lind, Associate Professor, Lund University, Sweden

Extraction of oxide traps in III-V MOSFETs using RF transconductance measurements

*Hui Jung Wu, Senior Technologist, Lam Research, USA

Advanced Cu-Low k Interconnect Extendibility and Reliability Challenges


*Lui Huang, Deputy Director of thin film, Global Foundary, USA

PMD and STI Gap-Fill Challenges for Advanced Technology of Logic and eNVM

*Rohan Akolkar, Professor, Case Western University, USA

Advances in Copper Electrodeposition for Interconnect Metallization


*Wan Chun Ren, Sr Engineer, SMIC, China

Thin film challenges of phase change random access memory

Symposium V: CMP, Wafer Substrate Polishing and Post-Polish Cleaning

**Dr. Manabu Tsujimura, CTO, Ebara Corporation, Japan

Enabling Solutions below 20 nm node

*Dr. Yongsik Moon, Manager CMP/Plating, GlobalFoundries, USA

Challenges in Chemical Mechanical Polishing for sub-20nm Logic Technology

*Prof. Ara Philiposian, Professor, University of Arizona, USA

Performance Analysis of A Novel Slurry Injection System for Oxide and Barrier Chemical Mechanical Planarization

*Dr. Reto Schoeb, CEO, Levitronix, Switzerland

Influence of Components in the Slurry Delivery Chain on Slurry Health and CMP Defects


*Dr. Zhihong Wang, Senior Technology Manager, Applied Materials, USA

Chemical Mechanical Polishing in TSV Applications

*Mansour Moinpour, Intel, USA

Surface Adsorption of CMP Slurry Additives on Abrasive Particles

*Ming-Shih Tsai, Senior Scientist, Cabot Microelectronic Corp., Britain 

Poly-Silicon Opening Polishing Slurry Development for Advanced HKMG Process

*Jinok Moon, Principal Engineer, Samsung, Korea

Layer by layer polymer assembly for scratch-free ceria slurry in CMP process

Symposium VI: Materials and Process Integration for Device and Interconnection

*Dr. Chih-Chao Yang, Senior Scientist/ Engineer, IBM, USA

Advanced Metallization for Future Cu/Low-k BEOL Technology

*Dr. Da Zhang, Senior Research scientist, Freescale, USA

Process variation impact on product characteristics

*Dr. Steven Demuynck, BEOL Integration Leader, IMEC, Belgium

Contacting advanced CMOS devices by local interconnects

*Prof. An-Quan Jiang, Professor, Fudan University, China

High-density Ferroelectric Resistive Memories

*Prof. D. Noel Buckley, Professor, University of Limerick, Ireland

In-situ Measurements of Stress and AFM during Electrochemical Deposition of Copper Nanofilms

*Prof. Kangwook Lee, Professor, Tohoku University, Japan

3D Integration Technologies and Reliability Challenges

*Prof. Zheyao Wang, Professor, Tsinghua University, China

Air gap through-silicon-vias

Symposium VII: Packaging and Assembly

*Dr. D.C. Hu, VP, Unimicron, China

The Next generation Substrate Material Challenges

*Dr. John Yuanlin Xie, Director, Altera Corporation, USA

Stacking Technology and Innovation Enabling the 2.5D Integration and Beyond

*Dr. Mark Huang, Director of Technology Development, Unisteel Technology Limited

Hermetic QFN Open Cavity Substrates for MEMS and SiP Packages

*Mr. Jin Yonggang, Manager, STMicroelectronics, Singapore

Embedded wafer level package development and characterization

*Mr. L.W Yong, CTO, Carsem in Malaysia, Malaysia

QFN technology Evolution


*Dr. Tim Chen, Genernal manager, Darbond Technology Co., Ltd, China

Thermal Management and Interface Materials Challenges of High Density and High Power IC Packages

*Prof. Johan Liu, Professor, Chalmers University of Technology, Sweden

Nanomterials for heat dissipation needs in packaging

Symposium VIII: Metrology, Reliability and Testing

**Dr. Assunta Vigliante, Head of Business Development for the Semiconductor Industry, Bruker AXS Inc. Germany

X-ray metrology for the advanced technology nodes

**Dr. Gennadi Bersuker, Fellow, Sematech, USA

Reliability assessment for advanced technology: Atomic - level models

*Dr. Baozhen Li, Senior Technology Member, IBM System and Technology Group, USA

Stress Migration Reliability for Advanced CU Interconnects

*Dr. Jinghong Li, Senior Engineer, IBM System and Technology Group, USA

Channel Strain Engineering and Characterization in Semiconductor Devices

*Dr. Ofer Adan, Global Product Manager and Technology Manager of metrology product line,  Applied Materials, USA

A novel electron microscopy approach to addressing on- product overlay challenges for advanced patterning while allowing re-work

*Prof. K.S. Chang Liao, Professor, National TsingHua University, China

Real-Time Measurement of Stress-Induced Interface Trap with Stress-and-Sense Charge Pumping

*Prof. Subhasish Mitra, Professor, Stanford University, USA

Robust System Design: Overcoming Complexity and Reliability Challenges


Symposium IX: Emerging Semiconductor Technologies

**Dr. Evangelous Eleftheriou, IBM Fellow, IBM Zurich Research Center, Switzerland

Multi-level phase-change memory

Bich-yen Nguyen, SOITEC, USA

*Dr. Laurent Dellmann, Research Staff Member, IBM Zurich Research Center, Switzerland

Carbon-based resistive random-access memory

*Dr. Christian Dussarrat, Director, Air Liquide, Japan

Design, synthesis of new precursors for semiconductor applications: a chemical supplier at the core of the semiconductor ecosystem

*Dr. Er-Xuan Ping, Managing Director, Applied Materials Inc., USA

3D Architecture Overview


*Prof. Dr. Hans Joachim Wuerfl, Professor, FBH, Germany,

Technological approaches towards high voltage fast switching GaN power transistors

*Prof. Jong-Hyun Ahn, Professor, Sungkyunkwan University, Korea

Graphene based flexible transistor

*Prof. Jae Min Myoung, Professor, Yonsei University, Korea

Handling  Nanomaterials for Electronic Device

*Prof. Jinn P. Chu, Vice Dean, Professor, National Taiwan University of Science and Technology, China

Reproducible and reliability of unipolar switching behavior in thin amorphous rare-earth scandate

*Prof. Kisuk Kang
, Professor, Seoul National University, Korea

Design of battery materials for portable electronics

*Prof. IIgu Yun, Professor, Yonsei University, Korea

Instability Assessment and Modeling of Amorphous InGaZno Thin Film Transistor under Alternating Pulse Bias Stress

*Prof. Ming Liu, Professor, Institute of Microelectronics, CAS, China

Microscopic mechanism of resistive switching memory: uncovering by transmission electron microscope characterization

*Prof. Nanjian WU, Professor, Institute of Microelectronics, CAS, China

Hign Speed Smart Image Sensors

*Prof. Seokwoo Jeon, Professor, Korea Advanced Institute of Science and Technology, Korea

Large Area, 3D Nanopatterned Templates for the Generation of Stretchable Electrodes

*Prof. SungWoo Nam, Assistant Professor, UIUC, USA

All-Carbon Graphene Electronics

*Prof. Tae-Woo Lee, Department Head, POSTECH, Korea

Flexible Organic Light-Emitting Diodes using Graphene Electrodes

*Prof. Yunqi Liu, Professor, Institute of Chemistry, CAS, China

Solution-processable organic semiconductors and their application in thin films transistors

Symposium X: Advances in MEMS and Sensor Technologies

**Dr. Madoo Varma, Director, Research Integrated Biosystems Lab, Intel, USA

Opportunities at the intersection of biology and silicon

*Dr.
Daniel J. Laser
, CEO, Wave 80, USA

Emerging Biomedical and energy aystems applications of ultraminiature high-power fluidic actuators


*Dr. Heinz-Peter Hippler, CEO,  IBD&E, Germany

Chinas Markets! - No Option for German SME?

*Dr. Li Gong, CEO, Suss Tech, China

New Development Exposure Optics of Mask Aligner 


*Dr. Satya Nitta, Manager, IBM T.J. Watson Research Center, USA

*Prof. Dr. J. G. E. Gardeniers, Professor, University of Twente, Netherlands

Microfluidic systems for the analysis of mass-limited samples

*Prof. Dr. Thomas Gessner, Director, Fraunhofer Institute for Electronic Nano Systems, Germany

Smart systems for a better life

*Prof. Inkyu Park, Professor, KAIST, Korea

Advanced chemical/physical sensing by hybrid 1D nanostructures


*Prof. Jing Chen, Professor, Peking University, China

Bulk titanium micromachining

*Prof. Ruifang Wang, professor, Xiamen University, China

Deep sub-nanosecond reversal of magnetic vortex in ferromagnetic nano-pits

*Prof.
Xiaohong Wang
, Professor, Tsinghua University, China

PowerMEMS based on Semiconductor Technologies and Nano Materials

*Prof. Yi-Kuen Lee, Associate Professor, HongKong University of Science and Technology, China

Predicting Electrophoretic Mobility of Large DNA Molecules in Semiconductor Biochips


*Prof.
Yang Zhao
, VP, MEMSIC, USA

Smart Sensor Network

*Prof. Zhiyu Hu, Professor, Nawei Energetic Research Institute, Shanghai University, China

Nanoscale Energy Conversion

*Prof. Zewen Liu, Professor, Tsinghua University, China

Solid-state nanopore fabrication with conventional process

Symposium XI: Circuit Design, System Integration and Applications

**Dr. Geoffrey Yeap, VP, Qualcom, USA

Advanced Technology-Design-Manufacturing Co-optimization for Smart Mobile Devices


**Mr. Mike Rieger, CTO, Synopsys, USA

**Dr. Serdar MANAKLI, CEO, Aselta Nanographics, France

Strategies for advanced Mask nodes: Resolution, Process, Cost Reduction


*Dr. Dake Liu, Professor, Linköping University, Sweden

Will ASIP replace ASIC in 2020 for highend embedded computing?

*Dr. Morris J. St Angelo, Director, IBM, USA

Advanced Analytics as an Empowerment to Predict and Improve Yields in Semiconductor and Electronic Component Manufacturing

*Dr. Neo Li, Senior H/W Development Manager, IBM's Design Center, China

High Performance ASIC design in IBM Advanced Technology

*Dr. Xu Ouyang, CEO, Semitronix, China

A highly efficient system for yield and variability learning  

*Dr. Yutao Feng, General Manager, Ambarella China, China

The "Consumerization" in the Network Surveillance Market

*Dr. Yuan Xie, Professor, Penn State University and AMD Research China Lab, USA

Modeling, Architecture, and Applications for Emerging Memory Technologies

*Prof. Guoyong SHI, Professor, School of Microelectronics, Shanghai Jiao Tong University, China

New Advances in Symbolic Network Analysis Methodologies for Design Automation of Analog Integrated Circuits and Systems

*Prof. Katherine Shu-Min Li, Associate Professor, National Sun Yat-Sen University, China

Algorithm/Architecture Co-Design for Multiple Scan Trees

*Prof. Masanori Hashimoto, Associate Professor, Osaka University, Japan

Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability 

*Prof. Weikang Qian, Assistant Professor, University of Michigan-Shanghai Jiao Tong University Joint Institute, China

The Synthesis of Digital Computation on Stochastic Bit Streams

*Prof. Yiyu Shi, Assistant Professor, Site Associate Director, NSF I/UCRC Net-Centric Software & Systems (NCSS) Center, Electrical and Computer Engineering Department, Missouri University of Science and Technology, USA

Through-Silicon-Via Placement for Three-Dimensional Integrated Circuits: A Thermal Perspective


 

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