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Plenary Session

CSTIC 2014,  Sunday, March 16, 2014

SHICC 上海国际会议中心 
中国上海浦东滨江大道2727号

08:45 – 09:35 Opening Ceremony,
  Opening Remarks by Conference Chair
  Opening Remarks by SEMI
  Opening Remarks by ECS
  Opening Remarks by Chinese Government Representatives
  Presentation of  ECS Best Student Paper Awards and SEMI Best Young Engineer Paper Awards
   
09:35 – 10:20


Dr. Tzu-Yin Chiu
CEO and Executive Director, SMIC
Challenges and Opportunities in Technology R&D for China Market

   
10:20 – 10:40 Coffee Break
   
10:40 – 11:20


Dr. Tak H. Ning
IBM Fellow and Member of US National Academy of Engineering, IBM Thomas J. Watson Research Center, USA
A Perspective on Low-Voltage Nanoelectronics

   
11:20 – 12:00


Dr. Kevin Zhang
Intel Fellow and vice president in the Technology and Manufacturing Group, Intel Corporation

Circuit Design in Nano-Scale CMOS Era: Challenges & Opportunities
   
12:00 – 13:30  
   

 Parallel Symposium Oral Sessions

 Sunday, March 16, 2014

   

13:30 – 17:00

Parallel Symposium Oral Sessions,

   

17:00 – 18:30

Conference Poster Session,

 
Monday, March 17, 2014

8:00 –18:30

 

  Parallel Symposium Oral Sessions

 

   
   

Symposium II & XI Joint sessionms


Shanghai International Convention Center

Meeting Room:3H+3I+3J

 

Session chairs: Kafai Lai/Jinjun Xiong

 

 

**8:45-9:15

High sigma modeling for analog and custom circuits

Lei He, University of California, Los Angeles

 

 

*9:15-9:35

The role of lithography enhancements in future device node scaling

 

Kevin Lucas,Synopsys, USA

 

 

9:35-9:55

Regardless of how you do it (Commercial, Captive, JV) reticles continue to drive technology
Paul Ackmann,Global Foundries

Symposium IV & VI Joint sessionms

Shanghai International Convention Center

Meeting Room: 3H+3I+3J

Session Chairs:Shaofeng Yu, Beichao Zhang

   

**10:15-10:45

Atomic Layer Deposition Trends and Challenges in High-k/Metal Gate and Alternative Channel CMOS Processing
Mike Chudzik, IBM

 

**10:45-11:15

Precision Materials Engineering to Meet FinFET Scaling Challenges Beyond 14nm

 

Adam Brand, Advanced Product Technology Development at Applied Materials Silicon Systems

   

**11:15-11:45

2D semiconductors for microelectronics and optoelectronics
Junqiao Wu, UC Berkeley

   

**11:45-12:15

A Study of Bulk FinFET Integration Process for 16nm node and beyond

 

Huilong Zhu, Institute of Microelectronics, Chinese Academy of Science

   

 

 


 Symposium I: Device Engineering and Technology

Symposium II: Lithography and Patterning

Symposium III: Dry &Wet Etch and Cleaning

Symposium IV: Thin Film Technology

Symposium V: CMP and Post-CMP Cleaning

Symposium VI: Materials and Process Integration for Device and Interconnection

Symposium VII: Packaging and Assembly

Symposium VIII: Metrology, Reliability and Testing

Symposium IX: Emerging Semiconductor Technologies

Symposium X: Advances in MEMS and Sensor Technologies

Symposium XI: Circuit Design, System Integration and Applications

Symposium XII: Si Materials and Photovoltaic Technology
 
Conference Banquet

Sunday, March 16, 2014
 Banquet fee

 

800RMB/Person     
Online Registration link;
(
http://223.4.179.170/semi2014/Visitor/Conference.aspx?lang=en&uid=)
 

19:00 – 21:00 Conference Banquet, 俏江南正大店(http://www.southbeauty.com/)
上海市浦东新区陆家嘴西路168号正大广场10F

 Hotel Floor Layout



 

 


 

 

 



 

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